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| PRELIMINARY CY3LV512/010 512K / 1 Mbit CPLD Boot EEPROM Features * EE Reprogrammable 524,288 x 1- and 1,048,576 x 1-bit Serial Memories Designed to Store Configuration Data for Complex Programmable Logic Devices (CPLDs) * In-System Programmable via two-wire Bus using Cypress's CYDH2200E Programming Kits * Simple Interface to SRAM-based CPLDs * Compatible with Cypress Delta39KTM & Quantum38KTM CPLDs * Cascadable Read-Back to Support Higher-density CPLDs * Low-power CMOS EEPROM Process * Available in PLCC Package (Pin Compatible Across Product Family) * Operate at 3.3V VCC * System-friendly READY Pin * Low-power Standby Mode Block Diagram CEO (A2) Cypress Semiconductor Corporation Document #: 38-03002 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 28, 2002 PRELIMINARY Functional Description The CY3LV512/010 (high-density CY3LV Series) CPLD boot EEPROMs provide an easy-to-use, cost-effective configuration memory for Complex Programmable Logic Devices. The CY3LV Series is packaged in the popular 20-pin PLCC. These devices support a system-friendly READY pin, which signifies a "good" power level to the CPLD and can be used to ensure reliable system power-up. The CY3LV Series boot PROMs can be programmed with industry-standard programmers or Cypress's CYDH2200E CPLD boot PROM programming kit. Please refer to the data sheet "CYDH2200E CPLD Boot PROM Programming Kit" for details. CY3LV512/010 Controlling the CY3LV CPLD Boot PROMs During Configuration Most connections between the CPLD device and the CY3LV boot PROM are simple and self-explanatory. Figure 1 shows the five signal interface required between the Delta39K/Quantum38K CPLD and the CY3LV boot PROM device. * The DATA output of the boot PROM drives DATA input of the CPLD * The master CPLD CCLK output drives the CLK input of the boot PROM * The CPLD CCE pin drives the CE input of the boot PROM * The RESET/OE input of the boot PROM is driven by the CPLD RESET pin * The READY pin of the boot PROM is connected to the RECONFIG pin of the CPLD The READY pin is available as an open-collector indicator of the device's RESET status; it is driven LOW while the device is in its POWER-ON RESET cycle and released (three-stated) when the cycle is complete. The rising edge of the READY (hence RECONFIG) signal causes the CPLD to start configuring. The CONFIG_DONE, CCE and RESET output of the CPLD are set LOW, CCLK is activated and CPLD starts receiving configuration data on the DATA pin. After all the configuration data is shifted in, the CPLD device deactivates the CCLK and sets CCE, RESET and CONFIG_DONE HIGH. A HIGH level on the RESET/OE input -- during CPLD reset -- clears the boot PROM's internal address pointer and subsequent reconfiguration starts at the beginning. The CEO output of any CY3LV drives the CE input of the next CY3LV in a cascade chain of EEPROMs. SER_EN must be connected to VCC, (except during In-System Programming). 3.3V CPLD Master Serial Mode Summary The I/O and logic functions of the CPLD and their associated interconnections are established by loading configuration data (bitstream) into the CPLD. This configuration data is loaded either automatically upon power-up, or upon issuing JTAGcommand. The configuration data is stored in the internal Flash memory (Self-Boot packages only) or in the external CPLD boot PROM memory. This data is loaded from the appropriate memory depending on the state of the CPLD mode select pin (MSEL). In Master Serial mode (when MSEL=1), the CPLD automatically loads the configuration program from an external memory i.e., CY3LV CPLD boot PROM. These PROMs have been designed for compatibility with the Master Serial Mode. This document discusses the interface between Cypress's SRAM based CPLDs (Quantum38K and Delta39K) and CY3LV PROMs. For more details on the other modes of configuration of these CPLDs please refer to the application note titled "Configuring Delta39K/Quantum38K." VCC VCCIO VCCJTAG VCCIO VCCPLL VCCCNFG VCC VCCPRG 4.7K 1K DATA Reset DELTA39K/ CCE QUANTUM38K CCLK TCLK TMS TDI TDO MSEL Reconfig Config_Done GND 1F SER_EN VCC DATA Reset/OE CE CLK GND READY CY3LV512/010 0.1F Figure 1. Interface between Delta39K/Quantum38K CPLD and CY3LV boot PROM Document #: 38-03002 Rev. *A 10-pins ISR Header Page 2 of 9 PRELIMINARY Note: Currently, 3 revisions of Delta39K100 and 2 revisions of Quantum38K100 devices are available marked as CY39100Vxxx, CY39100VxxxA, and CY39100VxxxB, CY38100Vxxx, and CY38100VxxxB. Figure 1 set-up represents the interface between CY39100VxxxB/CY38100VxxxB and CY3LV device. To get details on interface between other versions and CY3LV please refer to the application note titled "Configuring Delta39K/Quantum38K." Setup in Figure 1 also represents the interface between all other devices in Delta39K/Quantum38K families and CY3LV boot PROMs. CY3LV512/010 CY3LV Series RESET Polarity The CY3LV Series CPLD boot PROMs allow the user to program the reset polarity as either RESET/OE or RESET/OE.Cypress's SRAM based CPLDs (Delta39K and Quantum38K) require the RESET pin to be programmed active-High, i.e. as RESET/OE. CY3LV boot PROMs are shipped from the factory with the reset polarity programmed active-High. This polarity can be verified using industry standard programmers or Cypress's CYDH2200E boot PROM programming kit. Note: Every time the boot PROM is reprogrammed, care should be taken to select the reset polarity to be "HIGH" programmer software. Cascading CY3LV CPLD boot PROMs For future CPLDs requiring larger configuration memories, cascaded CPLD boot PROMs provide additional memory. As the last bit from the first boot PROM is read, the clock signal to the boot PROM asserts its CEO output LOW and disables its DATA line driver. The second boot PROM recognizes the Low level on its CE input and enables its DATA output. After configuration is complete, the address counters of all cascaded boot PROMs are reset if the RESET/OE on each boot PROM is driven to its active (HIGH) level. Programming Mode The programming mode is entered by bringing SER_EN LOW. In this mode the chip can be programmed by the two-wire serial bus. The programming is done at VCC (3.3V nominal) supply only. The CY3LV parts are read/write at 3.3V nominal. Standby Mode The CY3LV enters a low-power standby mode whenever CE is asserted High. In this mode, the boot PROM consumes less than 0.5 mA of current at 3.3V with CMOS level inputs. The output remains in a high-impedance state regardless of the state of the OE input. Document #: 38-03002 Rev. *A Page 3 of 9 PRELIMINARY . Table 1. Pin Configurations 20-pin PLCC 2 4 5 Name DATA CLK WP1 I/O I/O I I CY3LV512/010 6 RESET / OE I 7 WP2 I 8 CE I 10 14 GND CEO O A2 15 17 20 READY SER_EN VCC I O I Description Three-state DATA output for configuration. Open-collector bidirectional pin for programming. Clock input. Used to increment the internal address and bit counter for reading and programming. WRITE PROTECT (1). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during CPLD loading operations. RESET/Output Enable input (when SER_EN is HIGH). A LOW level on both the CE and RESET/OE inputs enables the data output driver. A HIGH level on RESET/OE resets both the address and bit counters. The logic polarity of this input is programmable as either RESET/OE or RESET/OE. Delta39K/Quantum38K CPLDs require this pin to be programmed as RESET/OE hence this document describes the pin as RESET/OE. WRITE PROTECT (2). Used to protect portions of memory during programming. Disabled by default due to internal pull-down resistor. This input pin is not used during CPLD loading operations. Chip Enable input. Used for device selection. A LOW level on both CE and OE enables the data output driver. A HIGH level on CE disables both the address and bit counters and forces the device into a low-power standby mode. Note that this pin will not enable/disable the device in the two-wire Serial Programming Mode (i.e., when SER_EN is LOW). Ground pin. A 0.1 F decoupling capacitor between VCC and GND is recommended Chip Enable Output. This signal is asserted LOW on the clock cycle following the last bit read from the memory. It will stay LOW as long as CE and OE are both LOW. It will then follow CE until OE goes HIGH. Thereafter, CEO will stay HIGH until the entire EEPROM is read again. Device selection input, A2. This is used to enable (or select) the device during programming (i.e., when SER_EN is LOW). Open collector reset state indicator. Driven LOW during power-up reset, released when power-up is complete. (Recommend a 4.7 k pull-up on this pin if used). Serial enable must be held High during CPLD loading operations. Bringing SER_EN LOW enables the two-wire Serial Programming Mode. +3.3V power supply pin. Pin Configurations NC DATA NC VCC NC 3 2 1 20 19 NC GND NC NC NC Document #: 38-03002 Rev. *A 9 10 11 12 13 CLK WP1 RESET/OE WP2 CE 4 5 6 7 8 18 17 16 15 14 NC SER_EN NC READY CEO (A2) Page 4 of 9 PRELIMINARY Maximum Ratings (Above which the useful life may be impaired. For user guidelines, not tested.) Operating Temperature ............................... -55C to +125C Storage Temperature ................................. -65C to +150C CY3LV512/010 Voltage on Any Pin with Respect to Ground......................... -0.1V to VCC + 0.5V Supply Voltage (VCC)......................................-0.5V to +7.0V Maximum Soldering Temp. (10 sec. @ 1/16in.) ...........260C ESD (RZAP = 1.5K, CZAP = 100 pF) ............................ 2000V Operating Range [1] Range Commercial Industrial Military Ambient Temperature 0C to + 70C -40C to + 85C -55C to + 125C Junction Temperature 0C to + 90C -40C to + 125C -55C to + 130C CY3LV512/010 (VCC) 3.3V 0.3V 3.3V 0.3V 3.3V 0.3V 3.3V Device Electrical Characteristics Over the Operating Range Parameter VIH VIL VOH VOL VOH VOL VOH VOL ICCA IL ICCS High-level input voltage Low-level input voltage High-level output voltage (IOH = -2.5 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -2 mA) Low-level output voltage (IOL = +3 mA) High-level output voltage (IOH = -2 mA) Low-level output voltage (IOL = +2.5 mA) Supply current, active mode Input or output leakage current (VIN = VCC or GND) Supply current, standby mode Commercial Industrial/Military -10 Military 2.4 0.4 5 10 100 100 Industrial 2.4 0.4 Commercial Description Min, 2.0 0 2.4 0.4 Max, VCC 0.8 Unit V V V V V V V V mA A A A Document #: 38-03002 Rev. *A Page 5 of 9 PRELIMINARY . CY3LV512/010 Switching Characteristics for CY3LV512/010 (3.3V) Over the Operating Range Parameter TOE[2] TCE[2] TCAC[2] TOH TDF[3] TLC THC TSCE THCE THOE FMAX Description OE to Data Delay CE to Data Delay CLK to Data Delay Data Hold From CE, OE, or CLK CE or OE to Data Float Delay CLK Low Time CLK High Time CE Setup Time to CLK (to guarantee proper counting) CE Hold Time from CLK (to guarantee proper counting) OE High Time (guarantees counter is reset) MAX Input Clock Frequency Commercial Min. Max. 50 55 55 0 50 25 25 30 0 25 15 Industrial Min. Max. 55 60 60 0 50 25 25 35 0 25 10 Unit ns ns ns ns ns ns ns ns ns ns MHz Switching Characteristics for CY3LV512/010 (3.3V) when Cascading Over the Operating Range Parameter tCDF[3] tOCK[2] tOCE[2] tOOE[2] FMAX Description CLK to Data Float Delay CLK to CEO Delay CE to CEO Delay RESET/OE to CEO Delay MAX Input Clock Frequency Commercial Min. Max. 50 50 35 35 12.5 Industrial Min. Max. 50 55 40 35 10 Unit ns ns ns ns MHz 3.3V Ordering Information Memory Size 1M 512K Ordering Code CY3LV010-10JC CY3LV010-10JI CY3LV512-10JC CY3LV512-10JI Package Name 20J 20J 20J 20J Package Type 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier 20-Lead Plastic Leaded Chip Carrier Operating Range Commercial Industrial Commercial Industrial Notes: 1. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. 2. AC test load = 50 pF. 3. Float delays are measured with 5 pF AC loads. Transition is measured 200 mV from steady state active levels. Document #: 38-03002 Rev. *A Page 6 of 9 PRELIMINARY AC Characteristics CY3LV512/010 AC Characteristics when Cascading Document #: 38-03002 Rev. *A Page 7 of 9 PRELIMINARY CY3LV512/010 Package Diagrams: 20J, 20-lead, Plastic J-leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters) Document #: 38-03002 Rev. *A Page 8 of 9 (c) Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY CY3LV512/010 Document Title: CY3LV512/010 512K/1 Mbit CPLD BOOT EEPROM DATASHEET (Preliminary) Document Number: 38-03002 REV. ** *A ECN NO. 106080 122216 Issue Date 08/07/01 12/28/02 Orig. of Change RN RBI New Data Sheet Power up requirements added to Operating Range Information Description of Change Document #: 38-03002 Rev. *A Page 9 of 9 |
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